Die attach paddle for mounting integrated circuit die

ABSTRACT

An electrical package for an integrated circuit die which comprises a die-attach paddle for mounting the integrated circuit die. The die-attach paddle has at least one down-set area located on a periphery of the die-attach paddle. The down-set area has an upper surface and a lower surface, with the upper surface configured to electrically couple a first end of a first electrically conductive lead wire. A second end of the first electrically conductive lead wire is bonded to the integrated circuit die. The upper surface is further configured to electrically couple a first end of a second electrically conductive lead wire and a second end of the second electrically conductive lead wire is bonded to a lead finger of the electrical package.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of and claims the benefit of priorityfrom U.S. patent application Ser. No. 10/965,653, filed Oct. 13, 2004which is hereby incorporated by reference.

TECHNICAL FIELD

The present invention relates to packaging of semiconductor integratedcircuits. More particularly, the present invention relates to a deviceand method for preventing electrical shorts between lead wires inintegrated circuit packaging.

BACKGROUND ART

As integrated circuit fabrication technology advances, the physical sizeof an integrated circuit device becomes progressively smaller. A givenwafer size can now produce more integrated circuit devices per waferwithout increasing a cost of wafer fabrication. One group of technicaldisciplines is aimed at packaging the devices. As devices become morecomplex and need to be integrated with additional devices, a universalinterconnection scheme becomes more difficult.

Typically, a semiconductor device has fixed input/output (I/O) lines andinterconnection with an external package can be difficult. Thisdifficulty may lead to a redesign of an entire integrated circuit toavoid long lead wires from the device to the package. Additionally, anylead lines that cross over each other have a potential for developing anelectrical short. Therefore, the interconnection of semiconductordevices with device packages is a major challenge in the art.

The integrated circuit devices are mounted on a surface of a mountingsubstrate and layers of interconnect lines and vias are formed thatconnect the devices to surrounding circuitry. Many different packagingapproaches are known and have been used for mounting and interconnectingsemiconductor devices, such as Dual-In-Line Packages (DIP), Pin GridArrays (PGA), Plastic Leaded Chip Carriers (PLCC) and Quad Flat Packages(QFP).

A maximum allowable bond wire length in package assembly is typically ina 3.8 mm-4.6 mm (150 mil-180 mil) range. However, with a smallerintegrated circuit die size, a distance between the die on the packagelead bond post increases since the standard packages tend to remain thesame size. This increase in distance between the integrated circuitpackage and the integrated circuit die can sometimes result in wireleads in excess of 5 mm (200 mil) or more. This long lead length cancreate assembly defects of wire-sweep during a molding operationresulting in potential electrical shorts between adjacent lead wires.

Currently, one solution is to convert the package into a stack-dieconfiguration. In this case, a bottom die has metal pads patterned to beused as “jumper” pads. A lead wire would be bonded from a top integratedcircuit die onto the bottom jumper die and then, in turn, to the packagelead. This breaks up the long wire into two shorter segments. However,this solution also requires design and fabrication of the jumper die.The jumper die, together with a stack die assembly, is a significantcost to a final assembled package.

FIG. 1A shows a cross-section of a typical integrated circuit die 101mounted into a lead frame package 100 (for example, a QFP). The leadframe package 100 includes a die-attach pad 103, die-attach adhesive105, a plurality of lead frames 107, electrically-insulating adhesive109, and a plurality of wire leads 111A. Once the plurality of bond wireleads 111A are connected from the integrated circuit die 101 to theplurality of lead frames 107, a mold compound 113 is used to encapsulateand complete the lead frame package 100.

FIG. 1B shows a bottom jumper die 115. A plurality of bond wire leads111B are connected from the integrated circuit die 101 to the bottomjumper die 115 and then to the plurality of lead frames 107, thuseliminating overly long bond wires.

An integrated circuit die, for example, a logic die, with 700 circuitsand three layers of wiring has approximately 5 m of aluminum wiring on achip less than 5 mm square. There are over 17,000 via connections fromlevel to level through an insulator film of SiO₂. Yet, the conductorcapacity in the die greatly lags behind the densification of the silicondevices. Most of the area of the die (approximately two-thirds), stillserves as a platform for wiring.

Therefore, what is needed is a is way to provide for flexible wiringtechniques between semiconductor devices and packages while avoidingproblems associated with long lead lines and potentially shorteddevices. Additionally, a universal package which may be used with avariety of different semiconductor devices is desirable.

DISCLOSURE OF THE INVENTION

The present invention eliminates the problem with long lead wires andjumper dice by forming a down-set area on a die-attach paddle to whichlead wires may be bonded prior to being connected to lead fingers (i.e.,the electrical “pins” of, for example, a quad flat pack) of theelectrical package. The die-attach paddle is an apparatus onto which anintegrated circuit die is mounted prior to a commencement of wirebonding operations. The present invention therefore comprises adie-attach paddle for mounting the integrated circuit die. Thedie-attach paddle has at least one down-set area located on a peripheryof the die-attach paddle. The down-set area has an upper surface and alower surface, with the upper surface configured to electrically couplea first end of a first electrically conductive lead wire. A second endof the first electrically conductive lead wire is bonded to theintegrated circuit die. The upper surface is further configured toelectrically couple a first end of a second electrically conductive leadwire and a second end of the second electrically conductive lead wire isbonded to a lead finger of the electrical package.

The present invention is also a method for attaching an integratedcircuit die to an electrical package. The method comprises forming adown-set on a periphery of a die-attach paddle and adhering theintegrated circuit die to an uppermost portion of the die-attach paddle.A first end of a first lead wire is bonded to the integrated circuit dieand the second end of the first lead wire is bonded to the down-setportion of the die-attach paddle. A first end of a second lead wire isbonded to the down-set portion of the die-attach paddle and a second endof the second lead wire is bonded to a lead finger of the electricalpackage. The integrated circuit die and die-attach paddle are thenencapsulated with, for example, an epoxy molding compound. Optionally,if the down-set area of the die-attach paddle is configured so as toprovide an electrical path between lead wires, any exposed lowermostsection of the down-set portion of the die-attach paddle is masked afterencapsulation. Exposed areas of the lead fingers are then plated with anelectrically conductive material. After plating, the lowermost sectionof the down-set portion of the die-attach paddle is then unmasked and alower section of the down-set portion of the die-attach paddle isremoved with a chemical etchant. Additionally, any conductive materialplated onto an uppermost surface of the down-set area is removed bychemical etching. Any void left by removing the conductive material andthe lower section of the down-set portion of the die-attach paddle isthen filled with epoxy.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a cross-section of a prior art integrated circuit package.

FIG. 1B is a cross-section of a prior art integrated circuit packageincorporating a jumper die.

FIG. 2 is a cross-section of an exemplary embodiment of the presentinvention showing the die paddle down-set.

FIG. 3 is the die paddle down-set of FIG. 2 showing bond wire leadsattached.

FIG. 4 is the die paddle down-set of FIG. 3 after encapsulation.

FIG. 5 is the die paddle down-set of FIG. 4 incorporating a temporarymechanical mask to prevent plating onto an exposed area of the down-set.

FIG. 6 is the die paddle down-set of FIG. 5 after removal of thetemporary mechanical mask and etching of the exposed area of thedown-set.

FIG. 7 is the die paddle down-set of FIG. 6 after an etch of exposedplating.

FIG. 8 is the die paddle down-set of FIG. 7 after performing a voidfiller operation.

FIG. 9 is an exemplary flowchart for a method of mounting an integratedcircuit into an electrical package of the present invention.

MODES FOR CARRYING OUT THE INVENTION

The present invention will now be described with reference to preferredembodiments thereof. With reference to FIG. 2, a down-set is formed on aperiphery of a die-attach paddle 201. A section of a lead finger 203 isused to electrically couple the integrated circuit die 101 to otherparts of a printed circuit board (not shown). A typical material usedfor fabrication of the die-attach paddle 201 and lead finger 203 iscopper, although other materials may readily be employed. An uppermostsurface of both the die-attach paddle 201 and the lead finger 203 isplated with a conductive material 205. In one specific embodiment, theconductive material 205 is silver. Alternatively, another noble metal,such as gold or platinum, may be used for the conductive material 205provided that the conductive material 205 and the bond wire material,described infra, are dissimilar. The integrated circuit die 101 ismechanically fastened to the die-attach paddle 201 through the use of asuitable adhesive 207.

In FIG. 3, a bond wire 301 is attached from the integrated circuit die101 to the down-set portion of the die-attach paddle 201. A second bondwire 303 is in electrical communication with the tail of the first bondwire 301 and is attached from the down-set portion of the die-attachpaddle 201 to the conductive material 205 on the lead finger 203. Thisarrangement of running the bond wire 301 from the integrated circuit die101 to the down-set portion of the die-attach paddle 201 and then to thelead finger 203 eliminates a single long lead by breaking the lead wirepath into two shorter segments. The shorter segments are unlikely to beable to short together with other bond wire segments (not shown).

Wire bonding techniques are well-known in the industry and are used toattach fine lead wires, typically 25 μm to 75 μm (1 mil-3 mil) indiameter, from one bond pad to another to complete an electricalconnection in electronic devices. Lead wires are frequently made ofgold, aluminum, silver, or copper. Contemporary methods of wire bondinginclude wedge bonding and ball bonding. Both methods utilizethermocompression, ultrasonic, and/or thermosonic techniques.

A mold compound forms an encapsulated area 401 (FIG. 4) around the leadwire bonded die-attach paddle 201 and lead finger 203. Notice that theencapsulated area 401 leaves a lowermost portion of the down-set area ofthe die-attach paddle 201 exposed for later processing (to be described,infra).

With respect to FIG. 5, a plating operation (e.g., standard tin-lead orpure tin) serves to provide a plated area 503 adhered to the lead finger203 for subsequent soldering of a completed integrated circuit packageto a printed circuit board. A mechanical mask 501 prevents plating fromattaching to a lower-most section of the down-set portion of thedie-attach paddle 201. The mechanical mask 501 may be virtually anymaterial capable of standing the plating operation and which can bereadily removed after the plating operation is complete. After plating,the mechanical mask 501 is removed.

A chemical etchant is subsequently used to remove the lower-most sectionof the down-set portion of the die-attach paddle 201 (FIG. 6). Forexample, if copper is used to construct the die-attach paddle 201, acopper etchant will effectively remove an exposed area of the die-attachpaddle 201, leaving a void 601. Notice that, in this example, the copperetchant does not etch the plated area 503, nor does it etch theconductive material 205. An additional chemical etchant step is used toremove a lower-most portion of the conductive material 205, leaving alarger void 701 (FIG. 7). Notice that the tail and head of the bondwires 301, 303 are in full electrical communication with each other.However, the bond wire 301, 303 pair which was previously in electricalcommunication with all other pairs of bond wires (not shown) through anelectrical coupling provided by the die-attach paddle 201, are nowelectrically isolated from all other bond wire pairs.

Finally, with reference to FIG. 8, a nonconductive liquid epoxy 801 isused to fill the void 701 left by the chemical etching steps.

The exemplary flowchart 900 of FIG. 9 begins with forming 901 a down-seton a die-attach paddle. The down-set may be applied to one or more edgesof a die-attach paddle. Alternatively, the down-set area of thedie-attach paddle may have individual legs (i.e., one leg for each wirebond pair) which are electrically isolated from each other. In thiscase, chemical etching of lower portions of the down-set legs would benecessary.

An integrated circuit die is then attached 903 to an uppermost portionof the die-attach paddle and lead wires are bonded 905 from the die tothe down-set area and from the tail of the first lead wire to one ormore lead fingers. Standard molding procedures are then employed 907 toencapsulate the die, die-attach paddle, lead wires, and portions of thelead fingers.

If the down-set area of the die-attach paddle incorporates individual,electrically isolated legs, described supra, the process is complete.If, however, a standard die-attach paddle comprising an electricallyconductive material is used, optional steps are employed to electricallyisolate each of the sets of wire bond pairs from one another. Theseoptional steps include masking 909 a lower-most portion of the down-setarea, performing lead plating 911 (e.g., plating leads with tin-lead orpure tin), etching 913 (e.g., chemically or mechanically etching copperused to construct the die-attach paddle) a lower-most portion of thedown-set area, etching 915 (e.g. chemically or mechanically etching) anyconductive plating material (e.g., silver) that was used on thedie-attach paddle, and filling 917 any down-set void created by theetching processes with filler material (e.g., epoxy).

Although the detailed description and drawings describe a universalinterconnect die and applications of the same, one skilled in the artwill recognize that other embodiments can readily be contemplatedwithout departing from an intended scope of the present inventiondescribed. For example, although the die-attach paddle 201 (FIG. 2) andthe conductive material 205 plated thereon are shown as two separatematerials for sake of clarity, one skilled in the art can readilyenvision a single material which may serve both purposes. Therefore, amethod of fabrication of the present invention would change accordingly.Thus, the fabrication process described herein is merely exemplary.Other techniques and materials (e.g., laminates or ceramics) may bereadily employed and still be within a scope of the present invention.Further, a skilled artisan will recognize that the lead wire bond pairsneed not be individual wires, but may simply be one continuous wire inwhich a center portion of the wire is bonded to an uppermost portion ofthe down-set area of the die-attach paddle.

1. A packaging apparatus for an integrated circuit die, comprising: adie-attach paddle having a raised portion configured to be joined to theintegrated circuit die, a first sloped portion of the die-attach paddleextending from one end of the raised portion and a second sloped portionextending from another end of the raised portion; a first lower portiondisposed adjacent to the first sloped portion in a laterally andvertically offset position from the raised portion; and a second lowerportion disposed adjacent to the second sloped portion in a secondlaterally and vertically offset position from the raised portion.
 2. Thepackaging apparatus of claim 1 wherein the raised portion and the firstand second sloped portions comprise copper.
 3. The packaging apparatusof claim 1 wherein the die-attach paddle is a single member.
 4. Thepackaging apparatus of claim 1 wherein the first lower portion contactsthe first sloped portion and the second lower portion contacts thesecond sloped portion.
 5. The packaging apparatus of claim 1 wherein thefirst and second lower portions are configured to accommodate leadwires.
 6. The packaging apparatus of claim 1 wherein the integratedcircuit die is configured to have a first end of a first lead wirebonded thereto, the first lower portion is configured to have a secondend of the first lead wire and a first end of a second lead wire bondedthereto, and a first lead finger is configured to have a second end ofthe second lead wire bonded thereto.
 7. The packaging apparatus of claim6 wherein the integrated circuit die is configured to have a first endof a third lead wire bonded thereto, the second lower portion isconfigured to have a second end of the third lead wire and a first endof a fourth lead wire bonded thereto, and a second lead finger isconfigured to have a second end of the fourth lead wire bonded thereto.8. The packaging apparatus of claim 1 further comprising a conductivematerial plated on the raised portion and the first and second slopedportions.
 9. A packaging apparatus for an integrated circuit diecomprising: a die-attach paddle having a raised portion configured to bejoined to the integrated circuit die; a first lower portion configuredto attach lead wires; a first sloped intermediate portion joining theraised portion and the first lower portion, the first lower portionbeing laterally and vertically offset in relation to the raised portion;a second lower portion configured to attach lead wires; and a secondsloped intermediate portion joining the raised portion and the secondlower portion, the second lower portion being laterally and verticallyoffset in relation to the raised portion.
 10. The apparatus of claim 9wherein the first sloped intermediate portion opposes the second slopedintermediate portion.
 11. The apparatus of claim 9 wherein the firstlower portion has an upper surface, the upper surface configured to bonda first end of a first lead wire, and a second end of a second lead wirethereto, the integrated circuit is configured to have a second end ofthe first lead wire bonded thereto and a lead finger is configured tohave a second end of the second lead wire bonded thereto.
 12. Theapparatus of claim 11 wherein the second lower portion has an uppersurface, the upper surface configured to bond a first end of a thirdlead wire and a first end of a fourth lead wire thereto, the integratedcircuit is configured to have a second end of the third lead wire bondedthereto, and a lead finger is configured to have a second end of thefourth lead wire bonded thereto.
 13. The apparatus of claim 9 whereinthe first sloped intermediate portion extends from a first end of theraised portion and the second sloped intermediate portion extends from asecond end of the raised portion.
 14. The packaging apparatus of claim 9wherein the die-attach paddle is a single member.
 15. A electricalpackage for an integrated circuit die, comprising: a die-attach paddlehaving a raised portion configured to be joined to the integratedcircuit die, a first sloped portion of the die-attach paddle extendingfrom one end of the raised portion and a second sloped portion extendingfrom another end of the raised portion; a first non-conductive lowerportion disposed adjacent to the first sloped portion in a laterally andvertically offset position from the raised portion; and a secondnon-conductive lower portion disposed adjacent to the second slopedportion in a second laterally and vertically offset position from theraised portion.
 16. The electrical package of claim 15 wherein the firstnon-conductive lower portion comprises a non-conductive liquid epoxy.17. The electrical package of claim 15 wherein the first non-conductivelower portion comprises a non-conductive epoxy filled void.
 18. Theelectrical package of claim 15 wherein the die-attach paddle is at leastpartially encapsulated by an encapsulant.
 19. The electrical package ofclaim 15 further comprising an encapsulant encapsulating at least aportion of the die-attach paddle but not a lower surface of the firstnon-conductive lower portion and not a lower surface of the secondnon-conductive lower portion.